The present disclosure relates to optical proximity correction (OPC) or resolution enhancement technologies (RET).
Fabrication and design of semiconductor devices, such as integrated circuits, is becoming more and more challenging as semiconductor technology nodes are progressively decreasing to small feature sizes.
In a design flow for an IC, it is typical to transform design data into a physical design or layout that describes specific geometric elements. The geometric elements, which can include various types of polygons, define the shapes that will be created in various materials to manufacture the circuit. A GDSII file is a typical representation of a layout. The design defined by the layout is produced onto various layers disposed on a semiconductor substrate. In doing so, it is typical for there to be numerous optical lithography processes. As the technology nodes decrease however, accurately reproducing the layout is becoming more and more difficult as optical effects can cause unwanted distortions in the printed features. These distortions include regions, such as in a critical dimension (CD) feature, have poor fidelity with the design data (e.g., ripple, narrowing of the line, etc.).
To account for these distortions, or potential distortions, typical design flows include various optical proximity correction (OPC) operations, also referred to as resolution enhancement techniques (RET). These techniques include adding additional features onto a photomask defining the layout (e.g., scattering bars). These techniques also include adjusting a polygon or geometrical element of the layout so that the printed feature will more accurately reflect the desired feature. In typical OPC processes, the edges of the geometric elements (polygons) are divided into segments, and each edge segment is adjusted to reflect the desired modifications. The adjustment is typically performed based on deviation between the desired layout and a simulated printed layout. While performing OPC on layout design data can improve the fidelity of the lithographic process, OPC can be expensive in terms of time, resources (e.g., computing and engineering), and/or photomask complexity. For example, having smaller and smaller edge segments may improve the fidelity but the computational time and power needed to process these segments for a complex IC design may be problematic.
Therefore, while the typical methods of OPC are suitable, what are needed are OPC methods that provide for suitable fidelity while improving upon one or more of the above mentioned challenges.